As miniaturization of a multimedia reproducing apparatus is rapidly proceeded, a high quality display device is being mounted also in a mobile communication terminal having a multimedia reproduction function, and miniaturization of parts related to a display function also emerges as a crucial factor.
An interface apparatus should be provided between a control module and a display module to allow the display module to display electric signals containing multimedia data. A related art interface apparatus includes an interface apparatus for delivering image signals and an interface apparatus for delivering chip control signals, so that the number of pins for connection increases.
Therefore, since the interface apparatus requires a separate transmission line for transmitting chip control signals, it becomes an obstacle in miniaturization of a multimedia reproducing apparatus, and increases manufacturing costs.
FIG. 1 is a view explaining an interface apparatus provided to a display device.
Referring to FIG. 1, the display device includes a central processor 12, a timing controller and signal converter 14, a decoder 16, and an interface apparatus 10 for connecting the central processor 12, the timing controller and signal converter 14, and the decoder 16.
The central processor 12 transmits received data in the form of image signals and chip control signals in order to drive a display module, and controls respective elements of the display device.
The image signals include display signals and display control signals.
The display signals include red (R), green (G), and blue (B) signals. The display control signals include horizontal synchronization input (Hsync) signals, vertical synchronization input (Vsync) signals, data enable (DE) signals, and data clock (DCLK) signals. The chip control signals include chip select (CS) signals, serial clock (SCK) signals, serial data input (SDI) signals, and serial data output (SDO) signals.
The timing controller and signal converter 14 converts the display signals into analog signals when outputting display signals received from the central processor 12 to the display module, and controls the orders and positions of display signals output to the display module according to the display control signals, i.e., the Hsync signals, Vsync signals, DE signals, and DCLK signals.
For example, display control signals can be signals for informing polarities in order to drive the display module in a positive polarity (+) or negative polarity (−), a signal for informing a start point (a point at which a first pixel is designated) of data, or signals for controlling an internal power sequence.
The decoder 16 decodes CS signals, SCK signals, and SDI signals delivered from the central processor 12 to deliver the same to the display module, and delivers decoding results and SDO signals requesting necessary data from the display module to the central processor 12. Here, the SDO signals may not be used depending on the kind of the display device.
The interface apparatus 10 includes a plurality of transmission lines.
R, G, and B signals, which are display signals, have a data size of 6 bit, respectively, in the case where they have a RGB666 format, and are transmitted in parallel via corresponding transmission lines but the chip control signals are transmitted in series.
As described above, the interface apparatus 10 provided to the display device transmits display signals, display control signals, and chip control signals via corresponding transmission lines.
Therefore, lots of transmission lines for connecting the central processor 12, the timing controller and signal converter 14, and the decoder 16 are required.
Also, since the interface apparatus for transmitting chip control signals adopts a serial transmission method, a speed in which chip control signals are transmitted is slow, which slows down an overall operating speed of the display device.